Computer Organization COMPUTER SCIENCE 3RD SEMESTER SYLLABUS

Computer Organization COMPUTER SCIENCE 3RD SEMESTER SYLLABUS

Government of Karnataka Department of Technical Education Bengaluru

 



Course Title:    Computer Organization

Scheme (L:T:P) : 4:0:0

Total Contact Hours: 52

Course Code:

15CS32T

Type of Course: Lectures, Self Study & Student Activity.

Credit :04

Core/ Elective:

Core

CIE- 25 Marks                                                                                                         SEE- 100 Marks


 Prerequisites

Fundamentals of Digital electronics and basics of Computers and its peripherals.

 Course Objectives

Understand the organization of a computer with its various processing units, memory and peripherals.
 Course Outcome

On successful completion of the course, the students will be able to attain below Course Outcome (CO):

Course outcome

CL

Linked PO

Teaching Hours

CO1

Recognize and explain the functional units

of computers

R

1,2,10

02

CO2

Describe assembly languages and machine

instructions by analyzing how the data is stored and fetched from memory.

U, A

 

1,2,3,4,8,10

 

10

CO3

Explain     the                 execution           of                 complete instruction and bus organizations.

U

2,8,9,10

08

CO4

Identify                  various                  interrupt                  handling mechanism and buses.

U, A

1,2,3,8,9,10

10

CO5

Differentiate between different types of memories.

U, A

1,2,3,4,5,6,7,8,9,10

14

CO6

Discuss core architecture and pipelined concept.

U

2,10

08

 

Total sessions

52

Legends: R = Remember U= Understand; A= Apply and above levels (Bloom’s revised taxonomy)

 Course-PO Attainment Matrix

Course

Programme Outcomes

1

2

3

4

5

6

7

8

9

10

Computer Organisation

3

3

2

2

1

1

1

3

3

3


Level 3- Highly Addressed, Level 2-Moderately Addressed, Level 1-Low Addressed.
Method is to relate the level of PO with the number of hours devoted to the COs which address the given PO. If >40% of classroom sessions addressing a particular PO, it is considered that PO is addressed at Level 3
If 25 to 40% of classroom sessions addressing a particular PO, it is considered that PO is addressed at Level 2 If 5 to 25% of classroom sessions addressing a particular PO, it is considered that PO is addressed at Level 1
If < 5% of classroom sessions addressing a particular PO, it is considered that PO is considered not-addressed.



 Course Content and Blue Print of Marks for SEE

Unit No

 

Unit Name

Hour

Questions to be set for SEE

Marks Weightage

Marks Weightage (%)

 

R

U

A

A

 

I

Basic Structure Of

Computers

02

5

-

-

5

4

II

Machine Instructions

and Programs

10

-

20

8

28

18

III

Basic Processing Unit

08

-

22

-

22

15

IV

Input/Output Organization

10

-

18

10

28

18

V

The Memory system

14

-

20

18

38

30

VI

Processors and

Pipelining

08

-

24

-

24

15

 

Total

52

5

104

36

145

100





Functional Units, Input Unit, Memory Unit, Arithmetic and Logic Unit, Output Unit, Control Unit, Basic Operational Concepts, Bus Structures.


Memory Locations and Addresses , Byte Addressability, Big Endian and Little Endian Assignments, Word Alignment, Accessing numbers, characters and character strings, Memory Operations, Instruction and Instruction sequencing, Register Transfer notation, Assembly Language notation, Basic instruction types, Instruction execution and straight line sequencing, Branching, Condition codes, Addressing modes, Implementation of variables and constants, Indirection and pointers, Indexing and arrays, Relative addressing, Additional modes, Assembly Language, Assembler directives, Assembly and execution of programs, Basic Input- Output Operations.


Some Fundamental Concepts, Register transfers, Performing an Arithmetic or Logic operation, Fetching a word from memory, Storing a word in memory, Execution of a complete Instruction, Branch instructions, Multiple Bus Organization, Hardwired
 
Control(basic block diagram only), A complete processor, Basic organization of Micro programmed Control Unit.



Accessing I/O Devices, Interrupts, Interrupt Hardware, Enabling and Disabling Interrupts, Handling Multiple Devices, Controlling Device requests, Exceptions, Direct Memory Access, Bus arbitration, Buses, Synchronous bus, Asynchronous bus, Interface Circuits, Parallel port and Serial port (Basic concept only), Standard I/O Interfaces (Basic concepts only), Peripheral Component Interconnect (PCI) Bus , SCSI Bus( Basic concepts only), Universal Serial Bus (USB) ( Basic concepts only)


Some Basic Concepts, Semiconductor RAM Memories, Internal Organization of memory chips, Static Memories, Asynchronous DRAMs, Synchronous DRAMs, Structure of larger memories, Memory system consideration, Rambus memory, Read-Only Memories- ROM, PROM, EPROM, EEPROM, Flash Memory, Speed, Size and Cost, Cache Memories...


Processor- Introduction, Advanced processor technology, instruction set architectures, CISC scalar processor, RISC scalar processor, comparison CISC and RISC, super scalar processor (basic concept only), VLIW architecture, comparison of super scalar and VLIW, Multi core architecture
Pipelining- Introduction, pipeline principles-linear pipeline processor-Asynchronous model, synchronous model, Non linear pipeline processor, classification of pipeline processor

1. Computer Organization, Carl Hamacher, zvonko Vranesic and Safwat Zaky, McGraw
Hill, 5th edition ( Chapters 1, 2, 4, 5, 7, for UNIT I to UNIT V )
2. Advanced Computer Architecture (A practical approach ), Rajiv Chopra, S. Chand, Revised edition, reprint 2014, ISBN8121930774 - for UNIT VI page no 133 to 138 , 143 to 145 , 192 to 194 , 218 to 219 , 221 to 223

1. http://elearning.vtu.ac.in/06CS46.html
2. http://nptel.ac.in/courses/Webcourse-contents/IIT-%20Guwahati/comp_org_arc/web/
3. William Stallings, “Computer Organization and Architecture: Designing for Performance”, Eighth Edition, Pearson.
4. Computer architecture and organization , 4th edition , P Chakraborty , JAICO publishers
5. http://www.srmuniv.ac.in/downloads/computer_architecture.pdf
6. http://www.dauniv.ac.in/downloads/CArch_PPTs/CompArchCh06L01PipeLine.pdf



Note: The following activities or similar activities for assessing CIE (IA) for 5 marks (Any one)
 
Student activity like mini-project, surveys, quizzes, etc. should be done in group of 3-5 students.
1. Each group should do any one of the following type activity or any other similar activity related to the course and before conduction, get it approved from concerned course co- ordinator and programme co-ordinator
2. Each group should conduct different activity and no repeating should occur.


1

Conduct a survey on various types of processors available with their features and

submit a report.

2

List  out  the features of    8086 microprocessor and 8051 micro controller with respect to architecture and working.

3

Submit a report on hardware and software interrupts.

4

A Case study on Moore’s Law about the processors and submit a report.

5

Conduct a survey on types of memories and also about the cost and speed of

various memories with comparison.



 Course Delivery

The course will be delivered through lectures and Power point presentations/ Video

 Course Assessment and Evaluation Scheme

Method

What

To

who m

When/Where

(Frequency in the course)

Max Marks

Evidence collected

Course outcomes

Direct Assessment

CIE

IA

Students

Three IA tests (Average of three tests will

be computed)

 

20

 

Blue books

1 to 6

Student activity

05

Report

1 to 6

Total

25

 

 

SEE

End

Exam

End of the

course

100

Answer scripts

at BTE

1 to 6

Indirect Assessment

Student

Feedback on course

Students

Middle of the course

 

 

Feedback forms

1,2,3

Delivery of course

End of Course Survey

End of the course

 

 

 

 

Questionnaires

1 to 6 Effectiveness of Delivery of      instructions &       Assessment

Methods


Note: I.A. test shall be conducted for 20 marks. Average marks of three tests shall be rounded off

to the next higher digit.
 
Questions for CIE and SEE will be designed to evaluate the various educational components (Bloom’s taxonomy) such as:

Sl. No

Bloom’s Category

%

1

Remembrance

10

2

Understanding

50

3

Application

40


Note to IA verifier: The following documents to be verified by CIE verifier at the end of semester
1. Blue books (20 marks)
2. Student suggested activities report for 5 marks
3. Student feedback on course regarding Effectiveness of Delivery of instructions & Assessment Methods.

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