Computer Organization COMPUTER SCIENCE 3RD SEMESTER MODEL QUESTION PAPER

Computer Organization COMPUTER SCIENCE 3RD SEMESTER MODEL QUESTION PAPER


MODEL QUESTION PAPER (CIE)

Test/Date and Time

Semester/year

Course/Course Code

Max Marks

Ex: I test/6 th weak of sem 10-11 AM

III SEM

Computer Organization

 

20

Year: 2015-16

Course code:15CS32T

Name of Course coordinator :

Units:1,2 Co: 1,2

Note: Answer all questions

Questio

n no

Question

CL

C

O

PO

1

Describe the role of MAR, MDR , PC and IR.

(5)

R

1

1,2

2

Explain the role of buffer registers

(5)

R

1

1,2

3

Describe the Big-endian and Little-endian addressability

(5)

U

2

1,2

4

Explain straight line sequencing

OR

Describe register and absolute addressing mode.

(5)

U

2

1,2



 Format for Student Activity Assessment

DIMENSION

Unsatisfactory 1

Developing 2

Satisfactory 3

Good 4

Exemplary 5

Score

Collection of data

Does not collect any information relating to the topic

Collects very limited information; some relate to the topic

Collects some basic information; refer to the topic

Collects relevant information; concerned to the topic

Collects a great deal of information; all refer to the topic

3

Fulfill team’s roles & duties

Does not perform any duties assigned to the team role

Performs very little duties

Performs nearly all duties

Performs all duties

Performs all duties of assigned team roles with presentation

4

Shares work equally

Always relies on others to do the work

Rarely does the assigned work; often needs reminding

Usually does the assigned work; rarely needs reminding

Does the assigned job without having to be reminded.

Always does the assigned work without having to be reminded and on given time

frame

3

Listen to other Team mates

Is always talking; never allows anyone else to speak

Usually does most of the talking; rarely allows others to speak

Listens, but sometimes talk too much

Listens and contributes to the relevant topic

Listens and contributes precisely to the relevant topic and exhibit leadership qualities

3

 

 

 

TOTAL

13/4=3.25=4



TOTAL 13/4=3.25=4
*All student activities should be done in a group of 4-5 students with a team leader.
 
 
Diploma in Computer science & Engineering
III- Semester
Course Title: Computer Organization
Time: 3 Hours Max Marks: 100
PART-A
Answer any SIX   questions. Each carries 5 marks. 5X6=30 Marks
1) Explain the basic functional unit of a Computer.
2) Describe register and absolute addressing mode.
3) Write a note on register transfers.
4) Explain the concept of micro programmed control .
5) Explain how to enable and disable an interrupt.
6) Explain the use of PCI bus in the computer system.
7) Explain the Double-data-rate SDRAM concept.
8) Explain the concept of flash drives.
9) Compare super scalar verses VLIW.

PART-B
Answer any SEVEN full  questions each carries 10 marks. 10X7=70 Marks
1. 1. Explain with examples one-address, two-address and three-address instruction types.
2. Describe program-controlled I/O operation.
3. Illustrate with diagram arithmetic and logic operation.
4. Describe the working of DMA.
5. Explain the serial port interface.
6. Explain the operation asynchronous DRAM.
7. Describe the features of PROM, EPROM and EEPROM.
8. Illustrate with diagram memory hierarchy with respect to speed, size and cost.
9. Explain CISC scalar and RISC scalar processor.
10. Describe Arithmetic, Instruction and processor pipelining.

MODEL QUESTION BANK
Diploma in Computer Science & Engineering III Semester
Course Title: Computer Organization

CO

Question

CL

Marks

 

 

I

Explain the basic functional unit of a Computer.

R

 

 

05

Describe the role of MAR, MDR , PC and IR.

R

Explain in brief the basic operation concept between processor and the

memory.

R

Explain the significance of single bus structure.

R

Explain the role of buffer registers.

R

 

 

 

 

 

 

 

 

II

Explain byte addressability.

U

 

 

 

05

Describe the Big-endian and Little-endian addressability.

U

Explain the basic memory operation.

U

Explain straight line sequencing.

U

Write a note on conditional codes.

U

Describe register and absolute addressing mode.

U

Write a note on relative addressing.

U

Explain with examples one-address, two-address and three-address

instruction types.

U

 

 

 

 

10

Illustrate Branching concept with Example.

A

Illustrate with examples Indirect addressing.

A

Describe Indexed addressing with examples.

A

Explain different assembler directives.

U

Explain the execution of assembly language program.

U

Describe program controlled I/O operation.

U

Explain the significance of auto-increment and auto-decrement

addressing mode

U

 

 

 

 

 

III

Explain the different phases for instruction execution .

U

 

 

05

Write a note on register transfers.

U

Explain how a complete instruction is executed.

U

Write a note on Hardwired control unit.

U

Explain the concept of micro programmed control unit.

U

Explain single bus organization.

U

 

 

10

Illustrate with diagram arithmetic and logic operation.

U

Describe fetching a word from memory.

U

Explain multiple bus organization.

U

With block diagram explain complete processor.

U

 

Explain the memory-mapped I/O concept.

U

 

 

 

 

 

05

Illustrate program controlled I/O.

U

Write a note on interrupts.

U

Explain how to enable and disable an interrupts.

U

Write a note on vectored interrupts.

U

Explain the exception concepts with respect to I/O.

U

 

 

 

 

IV

Explain bus arbitration logic.

U

 

List the activities of an I/O interface.

U

Explain the use of PCI bus in the computer system.

A

Write a note on SCSI bus.

A

Explain the universal serial bus concept.

U

Illustrate with examples interrupt service routine.

A

 

 

10

Explain implementation of prioritized interrupts.

U

Describe the working of DMA.

U

Explain synchronous and asynchronous bus.

U

Explain with example parallel port connectivity.

A

Explain serial port interface.

A

 

 

 

 

 

 

 

V

Illustrate how to implement a static RAM memory cell.

A

 

 

 

05

Illustrate how to implement CMOS memory.

A

Explain the Double-data-rate SDRAM concept.

U

Write a note on Ram bus memory.

U

Explain the configuration of ROM cell.

U

Write a note on flash memory.

A

Explain the concept of flash drives.

A

Explain the significance of cache memory.

U

Explain the internal organization of memory chips.

U

 

 

 

10

Explain the operation of asynchronous DRAM.

U

Explain the operation of synchronous DRAM.

U

Explain static and dynamic memory system.

U

Explain the use of memory controller with diagram.

A

Describe types of ROM

A

Illustrate with diagram memory hierarchy with respect to speed, size

and cost

U

Explain the working of cache memory operations.

U

 

 

 

 

 

 

VI

Explain Architecture of RISC machine.

U

 

 

 

05

Compare CISC verses RISC.

U

Explain super scalar processor.

U

Compare super scalar verses VLIW.

U

List advantages of multi core architecture.

U

List the applications of multi core architecture.

A

Explain Non-linear pipeline processor.

U

Explain VLIW Architecture.

U

 

 

10

Explain CISC scalar and RISC scalar processor .

U

With neat diagram explain Multi core architecture.

U

Explain Asynchronous and synchronous model of linear pipeline

processor.

U

Describe Arithmetic, Instruction and processor pipelining.

U


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